1. Field of the Invention
The present invention relates to a DRAM operated simultaneously with a clock signal in a semiconductor memory, and in particular to a clock frequency multiplying apparatus which is capable of implementing a fast data transfer by multiplying a clock frequency by dividing a clock signal in an internal circuit of the DRAM into a critical path and a non-critical path by using a transmission clock signal for the critical path and a multiplied clock signal for the non-critical path, and enhancing an internal data transfer ratio.
2. Description of the Conventional Art
As shown in FIG. 1, in the RAM bus DRAM, externally inputted data, address and instruction are latched, and a data is controlled in accordance with a clock signal generated by an internal clock generator 1.
Namely, the data which are serially inputted through a data input buffer 2 are processed simultaneously with a clock signal for receiving a predetermined data, and transmitting received data to the memory through a data shift register 3 by a data packet unit.
At this time, the above-described operation is implemented based on a clock phase such as a critical path and a non-critical path.
Therefore, the internal operation of the DRAM is performed using one clock phase, so that the transfer speed and ratio of the data are significantly decreased.